1. Field of the Invention
The present invention relates to the field of digital electronic systems. More particularly, the present invention relates to the field of interface circuits used for the communication of information between two or more electronic domains or subsystems having different clock rates.
2. Related Art
Designs of computer systems and computer system architectures today can include the combination of one or more different subsystems with each subsystem having a different bus architecture. Subsystems are combined to facilitate the implementation of larger systems and typically known and standard subsystems are the ones selected for combining. By using known and standard subsystems, design time, manufacturing costs, design complexity, system maintenance and trouble shooting can all be reduced advantageously.
One standard bus architecture is the Peripheral Component Interconnect (PCI) bus standard. Computer systems can communicate with coupled peripherals using different bus standards including the PCI bus standard, or alternatively, using the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) bus standards. Recently, the IEEE 1394 serial communication standard has become a popular bus standard adopted by manufacturers of computer systems and peripheral components for its high speed and interconnection flexibilities. Each of the above communication standards communicates information (e.g., in data packets) at particular clock rates depending on the clock speed selected for the bus architecture.
Interconnected subsystems of an integrated circuit design do not necessarily communicate or operate at the same clock frequency. Due to the many bus architecture standards available within computer systems and communication systems, it is often the case that one computer (or device) of one bus standard or "clock domain" is coupled to and communicates with another computer (or device) of another bus standard having another different clock domain. Since the clock frequencies of these bus standards are not necessarily compatible, bridge circuits or "interface circuits" have been used in the prior art to generate special handshaking signals, or otherwise function, to allow communication from one clock domain to another. The interface circuit is physically coupled between the two clock domains and is thereby made available to receive and send data or control information between the clock domains.
There are several different types of interface circuits in the prior art. One type of interface circuit includes a dual ported memory unit (e.g., random access memory) that allows one clock domain to write data into the memory and then allows the other clock domain to read the data from the memory. However, a disadvantage of this solution is that it is very costly in terms of circuit complexity and integrated circuit size. In many applications, these interface circuits are not practical from cost or substrate area standpoints. Another solution introduces a first-in-first-out (FIFO) memory element into the interface circuit for receiving (at one end) information from one clock domain and sending (at the other end) the information to the other clock domain. This solution is disadvantageous because it introduces unwanted latency in the transfer of information from one clock domain to another. The latency typically increases linearly with the size of the FIFO memory unit.
FIG. 1A illustrates another interface circuit for providing handshaking signals between clock domains (domain 1 and domain 2). In this example case, domain 2 is operating at a clock speed faster than domain 1. Specifically, FIG. 1A illustrates circuitry for sending a request signal from domain 1 to domain 2 and FIG. 1B illustrates the circuitry for sending a corresponding acknowledge signal from domain 2 back to domain 1. Flip-flop circuit 10 is clocked by the clock signal of domain 1 over clock line 14. Flip-flop circuits 20 and 30 are both clocked by domain 2 having a second (and different) clock frequency which is applied at clock line 40. Dashed divider 25 divides the domains. A request signal from domain 1 is fed over line 12 to the data input of flip-flop circuit 10 and the request signal ("RQ") is asserted by the output of flip-flip 10 over line 16. Line 16 is coupled to the data input of flip-flip 20 which is coupled to flip-flop 30 in a double synchronization configuration 45. The request signal is then obtained by domain 2 at the output of flip-flop 30 over line 42. This interface circuit is disadvantageous because the double synchronizer circuit 45 adds unwanted delay in the communication of the request signal from domain 1 to domain 2 and thereby introduces an unwanted performance hit.
FIG. 1B illustrates the circuitry for sending a corresponding acknowledge signal ("AQ") from domain 2 back to domain 1 in response to the request signal and any data related thereto. Domain 2 is operating at a clock speed faster than domain 1. Flip-flop circuits 50 and 55 are clocked by the clock line 14 of domain 1 and are configured as a double synchronizer circuit 64 for capturing the acknowledge signal from domain 2. Flip-flop circuits 60 and 70 are clocked by line 40 of domain 2 and together, with OR gate 65 comprise a pulse stretcher circuit 62. OR gate 65 is coupled between flip-flip 70 and flip-flop 60 using line 74. The acknowledge signal is input over line 72 and is pulse stretched using the pulse stretcher circuit 62. In one example case, the clock rate of domain 2 is 33 MHz having a pulse width of 30 ns while domain 1 is clocked at 20 MHz having a pulse width of 50 ns. Therefore, the pulse stretcher circuit 62 acts to stretch the 30 ns acknowledge pulse to 60 ns which is within the proper timing period to be captured by domain 1 (having a 50 ns window).
The disadvantages of the interface circuitry of FIG. 1A and FIG. 1B are two fold. The double synchronization circuits 45 and 64 consume too much cycle time and thereby add unwanted performance degradation to the overall communication system. It would be advantageous to eliminate this signal delay. Secondly, the pulse stretcher circuit 62 is hardwired for a particular ratio of clock speeds between the two clock domains (e.g., 20 MHz and 33 MHz) and is therefore static and based on these clock rate ratios. This design is not particularly flexible for operating with domains of different clock rates. For instance, if domain 1 should be clocked at faster rate than domain 2, the design of FIG. 1B will fail or if the clock rate of domain 2 should double, then the design of FIG. 1B will fail. There is only a narrow band of clock rate ratios that is supported by the prior art design of FIG. 1B. It would be advantageous to provide an interface circuit that was dynamic and could support multiple clock rate ratios.
Accordingly, the present invention provides an interface circuit for providing handshaking signals between subsystem domains having different clock rates within an electronic system. The present invention provides an interface circuit without the performance degradation associated with double synchronization circuits. The present invention also provides an interface circuit having a design that is not static but rather supports multiple clock rate ratios automatically. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.